Address fault monitoring device and ATM switching device

Details Address fault monitoring device and ATM switching device Address fault monitoring device and ATM switching device

1999-06-14

2002-12-17

Chin, Wellington (Department: 2733)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S242000

Reexamination Certificate

active

06496506

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to an address fault monitoring device and an ATM (Asynchronous Transfer Mode) switching device, and more particularly, to an address fault monitoring device for monitoring faults associated with the occurrence of floating addresses which are unusable addresses and an ATM switching device for performing a cell routing-switching process.
(2) Description of the Related Art
ATM is a communication technique developed for public networks to accomplish, within one network, multimedia communications of data, voice, moving picture, etc. at respective required rates while maintaining respective required qualities, and has been accepted as the foundation of next-generation information communications.
Material techniques for achieving ATM communications include cell switching technique. The cell switching technique is a technique of distributing asynchronously arriving cells at high speed according to their destinations, and is implemented by an ATM switching device having a hardware-based self routing-switching function.
FIG. 10
illustrates a schematic arrangement of a conventional ATM switching device. An ATM switching device
100
constitutes a common buffer-type ATM switched speech channel.
A cell multiplexing section
101
multiplexes cells transmitted thereto from input routes #
1
to #N. A write control section
102
performs write control on cells arriving at a rate of V from the N input routes, to write the cells once into a common memory
103
at a rate of V×N.
A read control section
104
receives, from the write control section
102
, write address information wd including information on addresses of the common memory
103
in which cells have been written, and stores the addresses in an address management FIFO
105
corresponding to output routes #
1
to #N to which the cells are to be output.
In accordance with the addresses managed by the address management FIFO
105
, the read control section
104
reads out the cells from the common memory
103
.
In this case, read addresses of the common memory
103
are sent to the write control section
102
as read address information rd to be used for subsequent write operations.
A cell separating section
106
separates and outputs the cells read out from the common memory
103
according to their respective output routes.
The above components are constructed on respective integrated circuits. For example, the cell multiplexing section
101
, the cell separating section
106
and the common memory
103
are constructed on LSIa, the write control section
102
is constructed on LSIb, and the read control section
104
is constructed on LSIc.
Accordingly, data is transmitted between the LSIs, and in order to ensure reliability of data transmission/reception, error correction needs to be made. In
FIG. 10
, error correction codes (parity information P) are exchanged between LSIb and LSIc.
If the read control section
104
detects a parity error while receiving the write address information wd, it does not read out the cell data then written into the common memory
103
at the corresponding address. An address like this which has ceased to be used due to transmission error or the like is called floating address.
Similarly, if the write control section
102
detects a parity error while receiving the read address information rd, the address (which becomes a floating address) then read out from the common memory
103
is not used thereafter as a write address.
Thus, if parity error occurs frequently, the number of floating addresses increases, reducing the storage area of the common memory
103
.
Conventionally, therefore, a fault monitoring section is provided so that faults such as parity error or out-of-synchronism may be monitored by means of firmware.
However, with the conventional measures to cope with faults, those faults occurring at intervals shorter than the fault processing period of the firmware fail to be detected, and thus the number of occurrences of fault, if counted by the firmware, cannot be detected with accuracy.
Accordingly, if the firmware counts only one occurrence of fault though a plurality of floating addresses have occurred, a large number of floating addresses can possibly be created.
Seemingly, therefore, the maximum band of the overall system gradually narrows, giving rise to a problem that the common memory
103
overflows.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide an address fault monitoring device capable of efficiently monitoring faults and quickly performing a counter-fault process.
A second object of the present invention is to provide an ATM switching device capable of efficiently monitoring faults and quickly performing a counter-fault process.
To achieve the first object, there is provided an address fault monitoring device for monitoring faults associated with occurrence of floating addresses which are unusable addresses. The address fault monitoring device comprises data storing means for storing data transmitted thereto, write control means for controlling writing of the data with respect to the data storing means and notifying a read control side of write address information including information on a write address, read control means for controlling reading of the data with respect to the data storing means and notifying the write control means of read address information including information on a read address, floating address measuring means for counting the number of the floating addresses by means of hardware, the floating address measuring means reckoning the write address or the read address as the floating address if transmission error occurs during transmission of the write address information or the read address information, and fault notifying means for monitoring the counted number of the floating addresses to determine whether or not the counted number is greater than a preset threshold, and making notification of fault if the counted number has become greater than or equal to the preset threshold.
To achieve the second object of the present invention, there is provided an ATM switching device for performing cell routing-switching process. The ATM switching device comprises a cell buffer for storing a cell transmitted thereto, write control means for controlling writing of the cell with respect to the cell buffer and notifying a read control side of write address information including information on a write address, read control means for controlling reading of the cell with respect to the cell buffer and notifying the write control means of read address information including information on a read address, floating address measuring means for counting the number of floating addresses, which are unusable addresses, by means of hardware, the floating address measuring means reckoning the write address or the read address as the floating address if transmission error occurs during transmission of the write address information or the read address information, and fault notifying means for monitoring the counted number of the floating addresses to determine whether or not the counted number is greater than a preset threshold, and making notification of fault if the counted number has become greater than or equal to the preset threshold.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.


REFERENCES:
patent: 6009078 (1999-12-01), Sato
patent: 6034959 (2000-03-01), Mizukoshi et al.
patent: 5-252183 (1993-09-01), None
patent: 7-288925 (1995-10-01), None
patent: 8-088636 (1996-04-01), None

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