Boots – shoes – and leggings
Patent
1986-11-07
1989-01-03
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1206
Patent
active
047961775
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to an address extension system in a processor of a data processing unit.
A system for dividing an address space into predetermined logical address spaces, i.e., segments, and generating a physical address as a sum of a starting point address of a segment and a relative address, i.e., an offset, has been recently adapted as a memory access system.
For example, a 16-bit processor has a 16-bit segment register and can direclty designate a 64-k byte address space. The 64-k byte address space is determined as a space for a segment. A physical address is obtained and generated by summing a starting point address of the segment and an offset.
However, since the address space which can be designated by the 16-bit starting point address is limited, the starting point addresses are shifted by adding a predetermined number of "0"s to the least significant bit (LSB) of the 16-bit addresses within the processor. For example, a 4 bit shifting is carried out so that the starting point addresses are extended to 20 bits, which corresponds to 1M byte.
In the above system, when the shift amount is increased, a maximum 32-bit address space can be obtained. However, the segment interval is expanded, and since the shift amount is predetermined, storage segments cannot be arbitrarily set for each program.
Generally, a processor has: an arithmetic and logic unit ALU; a segment register for storing a starting point address of a segment which is being executed; a program counter for indicating an offset being executed; a plurality of registers, and the like, such as a control register; an adder, an address buffer for temporarily storing an address signal; a data buffer, and an instruction decoder for decoding an instruction.
In the processor having the above arrangement, a physical address, generated by summing contents of the segment register and the program counter by the adder, is used for accessing a memory through the address buffer. An instruction, data, or the like, which is stored in the memory is read out and is decoded by the instruction decoder, and a designated logical operation is performed. Subsequently, the program counter is set to a next address, and processing is continued in accordance with the above procedure.
In the above operation, the initial values of the segment register and the program counter are set by an operating system OS when a program to be executed is loaded. When the processor is a 16-bit machine, the segment register, the program counter, the register, and the like, generally comprise 16 bits, and the 1-M byte address space is obtained by shifting the content of the segment register by 4 bits and summing it with the content of the program counter.
In the above summing, 4 "0"s are added to the least significant bit (LSB) of the segment register and the obtained content is summed with the value of the program counter. As a result, the segment starting point addresses are extended to 20 bits, the selection is carried out per 4 bits (which corresponds to per 16 bytes), and the selection concerning up to 1M byte becomes possible.
In the above system, when the address space is to be extended due to an increase in the memory capacity of the control unit, the shift amount may be increased. However, the shift amount is predetermined. When the shift amount is set at a maximum, the intervals of possible segment start point addresses are increased. Therefore, when a maximum address space is not used, the range of selection for storage segments for each different program is narrowed, resulting in a non-used area in the memory.
In consideration of the above situation, an address extension system wherein an address space can be extended and segments can be arbitrarily set has been desired. However, until the present invention a satisfactory system has not been available.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain an improved address extension system in a processor, wherein the shift amount of a programmable segment st
REFERENCES:
patent: 4092715 (1978-05-01), Scriver
patent: 4117263 (1978-09-01), Yeh
patent: 4215402 (1980-07-01), Mitchell et al.
patent: 4361868 (1982-11-01), Kaplinsky
patent: 4395764 (1983-07-01), Matsue
patent: 4453212 (1984-06-01), Gaither et al.
Nishimura Hisayuki
Shibata Tomochika
Chun Debra A.
Fujitsu Limited
Shaw Gareth D.
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