Address error detection technique for increasing the reliability

Details Address error detection technique for increasing the reliability Address error detection technique for increasing the reliability

1993-12-06

1995-02-21

Beausoliel, Jr., Robert W.

Excavating

G06F 1110, H03M 1300

Patent

active

053923022

ABSTRACT:
A fault detection arrangement provides error detection and verification of generated address sequences for the execution of read/write operations in a storage subsystem. The arrangement also prevents corruption of data stored on the subsystem array module. Gray code counters located in the address path of the array module generate sequential addresses and associated parity for words of a block of data, based on a starting address received from a storage controller. As each address is generated and transferred to storage devices of the array, a parity checker regenerates parity information associated with the transferred address and compares that parity information to the parity information received from the counters. If an address error is detected, execution of the read/write operation is suppressed and the controller is immediately notified of the error.

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IBM Technical Disclosure Bulletin, vol. 32, No. 3B; Aug. 1989; p. 44.

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