Address detection circuit using a memory

Details Address detection circuit using a memory Address detection circuit using a memory

1991-04-26

1994-06-07

Gossage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

36518907, 365 49, 36523001, 370 601, 370 941, 34082552, 395400, G06F 1200, H04J 324, G11C 800

Patent

active

053197640

ABSTRACT:
An address detection circuit for high speed detection of long addresses which utilizes a memory which is addressable at a shorter address length than the length of the address to be detected includes a subfield address generator which generates N (N being an integer greater than 1) subfield addresses obtained by dividing an input address by N. A subfield indicating signal generator generates a subfield indicating signal for indicating the order in which the N subfields are inputted. The subfield and subfield indicating signal form a memory address, which is generated N times. An address comparator compares the memory addresses and memory addresses stored therein and generates comparison signals. A decision circuit decides that when the comparison signals prove to be identity signals N number of times, the input address represents the address to be detected and generates an address detection signal.

REFERENCES:
patent: 4575818 (1986-03-01), Almy et al.
patent: 4769812 (1988-09-01), Shimizu
patent: 4815071 (1989-03-01), Shimizu
patent: 4907194 (1990-03-01), Yamada et al.

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