Address designating method of memory and apparatus therefor

Details Address designating method of memory and apparatus therefor Address designating method of memory and apparatus therefor

1982-12-02

1985-05-07

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 932

Patent

active

045162190

ABSTRACT:
An address designating method of a memory is performed by dividing the addresses of the memory to row addresses and column addresses. The writing of data in the memory is performed by the following steps. Namely, while the row addressing is maintained in a predetermined value (for example, 7d+1), the column addressing is incremented one by one. When the column addressing reaches 3, the row addressing is decremented by 4d+1. Each time the row addressing is decremented by d, the column addressing is decremented one by one in accord therewith. The reading of the data from the memory is performed by the following steps. Namely, each time the row addressing is incremented by d, the column addressing is also incremented one by one in accord therewith. When the column addressing reaches 3, the row addressing is decremented by 3d+1. With the row addressing kept in 0, the column addressing is decremented one by one.

REFERENCES:
patent: 4048624 (1977-09-01), Cochran et al.
patent: 4077058 (1978-02-01), Appeal et al.
patent: 4328543 (1982-05-01), Brickman et al.
patent: 4387424 (1983-06-01), Frediami et al.
patent: 4398264 (1983-08-01), Couper et al.

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