Address decoding scheme for DDR memory

Details Address decoding scheme for DDR memory Address decoding scheme for DDR memory

1998-03-30

2000-10-10

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365200, 36523004, 365233, 365236, G11C 800

Patent

active

061308536

ABSTRACT:
Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, in one cycle, two locations in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The circuits producing the two decoded outputs allow for sequential and interleaved mode, for data bursts of various lengths, and for addressing of redundant columns.

REFERENCES:
patent: 5610874 (1997-03-01), Park et al.
patent: 5629903 (1997-05-01), Agata
patent: 5663924 (1997-09-01), Barth, Jr. et al.
patent: 5920519 (1999-07-01), Jang

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