Address decoding circuit and method for addressing a regular...

Details Address decoding circuit and method for addressing a regular... Address decoding circuit and method for addressing a regular...

2005-12-20

2005-12-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S200000, C365S201000, C365S230030

Reexamination Certificate

active

06977862

ABSTRACT:
Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.

REFERENCES:
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Tanabe, Akira; Takeshima, Toshio; Koike Hiroki u.a.: A 30-ns 64 Mb DRAM with Built-in Self-Test and Self-Repair Function, IEEE J. Solid-State Circuits, Nov. 1992, vol. 27, No. 11, pp. 1525-1531.
German Patent Office Examination Report dated May 26, 2004.

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