Address decoder with small circuit scale and address area expans

Details Address decoder with small circuit scale and address area expans Address decoder with small circuit scale and address area expans

1994-07-26

1997-04-08

Moore, David K.

395416, 395419, 395413, G06F 1200, G06F 1202, G06F 926, G06F 934

Patent

active

056196709

ABSTRACT:
An address decoder has a plurality of address comparator circuits for respective address areas, each comparator circuit including a base address register, a mask register, an AND gate, and a comparator. An address data outputted from a processor is inputted to the address comparator where the AND circuit takes an AND logic of each bit for the address and an inverted value taken for each bit from the content of the mask register and the result is compared to a starting address of the pertinent address area stored in the base address register. If the compared data are in accord, an address decoded signal of "1" is outputted, which indicates that the address is an address within the pertinent address area. The address comparators and function in the same way as the address comparator. A priority encoder receives address decoded signals from the plurality of address comparator circuits and outputs a highest priority address decoded signal as a final output when it receives a plurality of in-accord address decoded signals. The address decoder is small in circuit scale and has address area expansion capability.

REFERENCES:
patent: 4075694 (1978-02-01), Ericsson
patent: 4488256 (1984-12-01), Zolnowski et al.
patent: 4903234 (1990-02-01), Sakuraba et al.
Soviet Patent Abstract AN 87-248615/35, Section EI, Week 8735, Derwent Publications Ltd. Sep. 9, 1987.
Patent Abstracts of Japan, vol. 13, No. 319 (P-901), Jul. 19, 1989.
Soviet Patent Abstract AN 87-248615/35 Sep. 1987.

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