Address decoder with memory allocation for a micro-controller sy

Details Address decoder with memory allocation for a micro-controller sy Address decoder with memory allocation for a micro-controller sy

1993-12-09

1996-06-25

Teska, Kevin J.

Boots, shoes, and leggings

39549701, 36446402, G06F 1206

Patent

active

055308406

ABSTRACT:
The micro-controller system is comprised of a programmable microprocessor, a plurality of memory units having a plurality of addressable memory registers. The memory units are in bus communication with the programmable processor and an application specific integrated circuit. The application specific integrated circuit includes a circuit for dividing the memory units into a plurality of addressable regions in response to programming of the programmable microprocessor. The microprocessor is programmed such that the initial address for each of the regions is assigned by the most significant address bits, and the uppermost address for the region being programmably defined by an uppermost address for the respective region. The circuit includes a plurality of addressable registers. The microprocessor can address each of the circuit registers and write a respective uppermost address in a respective one of the registers, the respective address corresponding to uppermost addressable registers of the respective addressable regions of the memory units.

REFERENCES:
patent: 4710882 (1987-12-01), DiGiulio et al.
patent: 4998203 (1991-05-01), DiGiulio
patent: 5305398 (1994-04-01), Klein et al.
patent: 5377344 (1994-12-01), Stager et al.
patent: 5426424 (1995-06-01), Vanden Heuvel et al.
patent: 5465343 (1995-11-01), Henson et al.

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