Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2008-03-25
2008-03-25
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189080
Reexamination Certificate
active
11385717
ABSTRACT:
The address decoder includes: a plurality of decode units each formed by a combinational logic circuit; an inverting circuit which inverts an output of said decode unit; an AND circuit which performs a logical AND operation between an output signal of said decode unit, which has been inverted by said inverting circuit, and another one of said plurality of decode units. This arrangement makes it possible to simplify the circuit construction, to improve the processing speed, and to reduce power consumption.
REFERENCES:
patent: 5673048 (1997-09-01), Kearney et al.
patent: 6026045 (2000-02-01), Son
patent: 6144612 (2000-11-01), Numasawa
patent: 6373752 (2002-04-01), Wright et al.
patent: 0 405 812 (1991-01-01), None
patent: 2002-63792 (2002-02-01), None
patent: 1994-12390 (1994-06-01), None
patent: 1998-072847 (1999-11-01), None
Extended European Search Report, mailed Jan. 5, 2007, and issued in corresponding European Patent Application No. 06251653.9-1233.
US 6,026,045 (Reference AA) corresponds to KR 1998-072847 (Reference AH).
Korean Patent Office Action, mailed Apr. 26, 2007 and issued in corresponding Korean Patent Application No. 10-2006-0033225.
Murata Seiji
Nakadai Hiroshi
Dinh Son
Fujitsu Limited
Staas & Halsey , LLP
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