Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-12-05
2003-03-04
Robertson, David L. (Department: 2187)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230060, C716S030000
Reexamination Certificate
active
06529396
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an integrated circuit memory having address decoders connected to address lines in an improved arrangement, a method of manufacturing an integrated circuit memory having such an improved arrangement of address decoders and a method of determining the connection between address decoders and address lines for such an improved arrangement.
BACKGROUND OF THE INVENTION
Memory arrays comprise storage elements or cells which are arranged in rows and columns. Rows are addressable by word lines which extend in a first direction and columns are addressable via bit lines which extend perpendicularly to the word lines. For convenience the word lines will be referred to hereinafter as running in the horizontal direction. Each word line is connected to a corresponding address decoder which upon receipt of a particular address asserts the corresponding word line. Normally, the address decoders are physically located adjacent the memory array in a vertical column. The address decoders receive the address via address lines which are commonly arranged such that they extend vertically (i.e. in the same direction as the bit lines) of the memory array. It has previously been known to arrange the address decoders such that the address decoder selected by the highest “value” of address word, i.e. 1111 for a four bit address, is connected to the first word line of the memory array with each subsequent address decoder being selected by the next highest “value” of address word, in ordered sequence. This arrangement of address decoders in ordered address word sequence means that the average propagation delay experienced by a signal propagating along the address line corresponding to the most significant bit of an address word is higher than the average propagation delay for the address line corresponding to the lowest significant bit. This will be explained in more detail hereinafter. The speed at which the address decoders can be operated at is therefore limited by the largest propagation delay on the most significant bit address line.
It is an aim of embodiments of the present invention to provide a method for arranging the address decoders in an improved manner so that the average propagation delay for each address line can be made more uniform, preferably the delay is minimised and made equal to each other. By reducing the maximum propagation delay in this way the speed at which the address decoders for a memory array can be operated at is increased.
SUMMARY OF THE INVENTION
According to the present invention there is provided an integrated circuit memory comprising: a plurality of storage elements arranged in rows and columns; a plurality of word lines, each word line connected to a respective row of storage elements and being connected to a respective address decoder; a plurality of address lines extending from address circuitry to said address decoders, each address decoder being connected to a certain combination of said address lines representing a certain address value to which the address decoder responds to assert its associated word line, wherein said address decoders are connected to said address lines in a manner which is out of order with respect to an ordered sequence of said address values.
Preferably the address decoders are arranged such that only one of the address lines is connected to adjacent ones of said address decoders.
According to the present invention there is also provided A method of manufacturing an integrated circuit memory comprising: a plurality of storage elements arranged in rows and columns; a plurality of word lines, each word line connected to a respective row of storage elements and being connected to a respective address decoder; and a plurality of address lines extending from address circuitry to said address decoders, the method comprising: connecting each of said address decoders to a certain combination of address lines representing a certain address value to which that address decoder responds, wherein said connecting step is carried out so as to arrange the address decoders out of order with respect to an ordered sequence of said address values.
According to the present invention there is further provided A method of determining the connections between a plurality of address decoders and a plurality of address lines in a memory array, said method comprising: denoting n pairs of address bits, wherein the nth pair of address bits are the least significant bits of an address word; defining n operations of said n pairs of address bits, each operation changing the value of the address word when performed on said address word, wherein each Kth operation, where K is an integer between 1 and n, comprises incrementing the Kth pair of address bits by one term of a 2 bit Gray code and inverting the remaining pairs of address bits; performing said n operations in a predetermined sequence wherein operation (K+1) is performed every 4K operations, otherwise operation 1 is performed, where K increments from 1 to (n−1), whereby a sequence of address words is generated wherein only a single bit has the same value for adjacent address words in said generated sequence of address words.
Preferably the average propagation delay of said address lines is substantially equal.
It will be appreciated that an ordered sequence denotes a sequence where the values to which each address decoder responds increases in an ordered manner between the address decoder connected to the lowermost word line and that connected to the uppermost word line.
For a better understanding of the present invention and as to how the same may be carried into effect, reference may now be made by way of example to the accompanying drawings in which:
REFERENCES:
patent: 5784330 (1998-07-01), Beck et al.
patent: 0 520 650 (1992-12-01), None
EPO, Standard Search Report for UK Appl. No. 9929372.2.
Jenkens & Gilchrist P.C.
Robertson David L.
STMicroelectronics Limited
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