Address decoder for a synchronous type memory capable of prevent

Details Address decoder for a synchronous type memory capable of prevent Address decoder for a synchronous type memory capable of prevent

2000-02-17

2000-11-07

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365233, 36523008, 326106, 326108, 326105, G11C 810, G11C 820

Patent

active

061446122

ABSTRACT:
Address decoder of the present invention includes a latch circuit for latching an address signal, a logical circuit for decoding output signal from the latching circuit and a decoding circuit for decoding an output signal from the logical circuit. The address signals are inputted to the latch circuit during a time period in which a clock signal is at a first level and latched during a time period in which the clock signal is at a second level. The logical circuits unconditionally initialize the output signal from the latch circuit when the clock signal being at first level.

REFERENCES:
patent: 5305277 (1994-04-01), Derwin et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5631577 (1997-05-01), Freidin et al.
patent: 5959936 (1999-09-01), Seo et al.

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