Address decoder circuits adjusted for a high speed operation at

Details Address decoder circuits adjusted for a high speed operation at Address decoder circuits adjusted for a high speed operation at

1996-04-12

1998-02-24

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523088, G11G 800

Patent

active

057217092

ABSTRACT:
A decoder circuitry is provided between input signal lines and word lines. The number of the word lines is larger than the input signal lines. The decoder circuitry comprises a plurality of stages including at least an input side stage adjacent to the input signal lines and an output side stage adjacent to the word lines. Each of the plurality of stages includes plural logic circuits. The plural stages so vary as not to decrease in the number of the logic circuits when the stage approaches to the word lines so that the number of the logic circuits in the input side stage adjacent to the input signal lines is smaller than the number of the logic circuits in the output side stage adjacent to the word lines. Each of the logic circuits has a plurality of field effect transistors. The field effect transistors so vary as not to decrease in absolute value of threshold voltage when the stage approaches to the word lines so that an absolute value of threshold voltage of the transistors provided in the input side stage adjacent to the input signal lines is smaller than an absolute value of threshold voltage of the transistors provided in the output side stage adjacent to the word lines.

REFERENCES:
patent: 5402377 (1995-03-01), Ohhata et al.

Affiliated with

Also associated with

Rating

Address decoder circuits adjusted for a high speed operation at does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address decoder circuits adjusted for a high speed operation at , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address decoder circuits adjusted for a high speed operation at will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1879056