Address decoder circuit for non-volatile memory

Details Address decoder circuit for non-volatile memory Address decoder circuit for non-volatile memory

1989-10-13

1991-08-13

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 3072962, 36523006, H03K 1716

Patent

active

050398822

ABSTRACT:
An address decoder circuit adapted for enabling electrical erasure in a non-volatile memory without the necessity of numerically increasing the component elements, wherein the direction of application (polarity) of a supply voltage during an erasing operation to a decoding logic gate portion comprising a load MOS transistor and an address input MOS transistor is rendered different from that during a writing or reading operation, and a third potential is applied to the power terminal proximate to the address input MOS transistor and also to the power terminal of a buffer, whereby the third potential is outputted to prevent erasure in the state of non-selection. The resistance of load means is changed to be greater in a writing operation for reducing the power consumption during the writing operation and minimizing the dimensions of component elements. And in a voltage supply circuit, for the purpose of outputting a desired voltage without providing any additional circuit which may consume great power or without causing any level reduction of a first or write voltage, a MOS transistor for outputting the first voltage is controlled in response to a signal obtained by boosting the voltage of a control signal through a voltage multiplier.

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Bello, "MOSFET Load Gate Controlled Driven," IBM T.D.B., vol. 15, No. 3, Aug. 1972.

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