Address decoder circuit

Details Address decoder circuit Address decoder circuit

1985-11-12

1987-03-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307463, 365189, 365230, G11C 8000, H03K 19094

Patent

active

046510311

ABSTRACT:
An address decoder circuit of the present invention forms a word line selection signal by entering an m-bit address signal by dividing it into two groups of i bits and (m-i) bits. The decoder output from the i-bit signal is inputted to the gate of a first enhancement-type MOS transistor and that from the (m-i)-bit signal is applied to its source. Its drain is connected to a word line of a memory cell array. An inverter is provided to invert the decoder output from the i-bit signal and the output from the inverter is applied to the gate of a second enhancement-type MOS transistor of which the drain and the source are connected respectively to the word line and a power source terminal.

REFERENCES:
"Two-Phase Dynamic Logic with Enhancement Depletion Technology" Falcoz et al.
"On-Chip Redundancy Scheme", Schuster.
"High-Density Multiemitter Transistor Decoder", Weidmann.

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