Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-05-16
2001-08-14
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189080, C365S189050
Reexamination Certificate
active
06275442
ABSTRACT:
TECHNICAL FIELD
The invention relates to computer memory systems generally. More particularly, the invention relates to testing and verification of memory address decoders and to memory address decoders that facilitate testing and verification.
BACKGROUND ART
In manufacturing semiconductor memory devices, the memory devices are generally screened prior to shipping by revealing latent failures of the memory devices. During screening, those memory devices having the possibility of initial failure are removed to ensure the reliability of the shipped semiconductor memory devices. One of such screening methods is accelerated stress testing, in which the memory devices are subjected to one or more of extreme electrical, environmental or other conditions for a period of time. An exemplary form of accelerated stress testing is “burn-in” testing, in which high temperature and high voltage are applied to a semiconductor device. During burn-in testing, a semiconductor device is operated with the applied voltage higher than a voltage applied in normal operation and with the ambient temperature higher than a temperature normally experienced, so that the semiconductor device experiences, within a very short period of time, stress greater than that caused during the initial failure period under practical conditions. Such screening efficiently identifies those semiconductor devices likely to experience infant mortality and thus improves the reliability of surviving devices.
To be effective, accelerated stress testing should be comprehensive in the sense that every node of a device should be tested while in a 0 state and a 1 state. In a semiconductor memory device with a large storage capacity, this requirement of comprehensiveness can cause the testing to take a very long time unless special testing accommodations are made. In the normal operation of a RAM (random access memory) device, each unique combination of input address lines activates, via an address decoder, a different word line, which accesses a different word in a memory array. Accelerated stress testing in the normal mode of operation requires that each different address be asserted sequentially (so called “address scanning”); at each address, an all-0 pattern is read and/or written, followed by an all-1 word (or possibly different pairs of complementary patterns). If the time required for effective accelerated stress testing of each node were X seconds, and the memory device contains Y words, then the total time for testing would be XY seconds. Because modem memory devices contain as many as 8,192 words or more, testing in the normal mode of operation is prohibitively time consuming. For example, if X=3 seconds and Y=8,192, the required testing time is nearly seven hours per device.
To reduce the time needed for accelerated stress testing of a memory array, it is known in the art to design the memory device to have a testing capability such that all word lines can be simultaneously activated. In this way, the entire decoder can be tested in one pass. However, this technique is not useful for accelerated stress testing of circuitry peripheral to the memory array, such as address decoders, which are speed critical. This problem is all the more poignant in a memory device designed for speedy access, such as a memory device intended for use as a cache to a microprocessor. In such cases, fast access is attributable to the address decoders and other peripheral circuitry rather than the memory array, and burn-in testing of the peripheral circuitry is especially important. Adding logic enabling the simultaneous activation of all word lines slows the address decoding and hence the memory system.
SUMMARY OF INVENTION
In one respect, the invention is a memory system comprising a decoder circuit. The decoder circuit accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each AND gate input is connected to a latch output, and each AND gate output is one of the plurality of word lines.
In another respect, the invention is a decoder accepting decoder inputs and producing decoder outputs. The decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs, which may be address lines. The outputs of each non-final stage is an input to a subsequent stage. The set of latches are connected to the outputs of a particular stage.
In yet another respect, the invention is a method for use with a decoder. The method processes a set of input signals, whereby a set of processed signals are generated. The method latches the processed signals. The latched signals may be decode lines, or the latched signals may be intermediate signals in a decoding operation, in which case the method optionally further processes the intermediate signals so as to complete the decoding operation. Optionally, in a testing mode, address scanning is rapidly applied to subsets of the set of input signals, whereby substantially all of the decoder circuitry is exercised and the latched signals are activated concurrently, thus enabling accelerated stress testing of the decoder in a brief time that is independent of the size of the decoder.
In comparison to the prior art, certain embodiments of the invention are capable of achieving certain advantages, including the following:
(1) Faster accelerated stress testing of the address decoder is possible because latching of an intermediate signal in the decoder allows for a non-sequential mode of operation.
Accelerated stress testing can be performed in a time that is independent of the size of the decoder's address space.
(2) Faster operation of the address decoder is possible, compared to prior art address decoders that employ logic gates in series in critical timing paths to provide accelerated stress testing.
(3) A minimum of semiconductor circuit area is required for the additional logic that facilitates faster accelerated stress testing.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.
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Hill J. Michael
Lachman Jonathan E.
Queen William J.
Hewlett--Packard Company
Le Thong
Phan Trong
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