Address decoder and address decoding method

Details Address decoder and address decoding method Address decoder and address decoding method

1997-07-08

1999-03-23

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365233, G11C 800

Patent

active

058869417

ABSTRACT:
There is provided an address decoder which allows a high-speed operation without causing a malfunction. When a pre-charge signal is in a state of being set at a logical level of "0", an address driver is brought into a state of being held at "1". When the pre-charge signal is in a state of being set to a logical level "1", the address driver outputs a drive signal pair which becomes positive phase and negative phase of an address signal to each of the drive signal lines. A detection circuit is connected to each signal line of at least one drive signal pair among a plurality of signal pairs at an end portion of the signal lines on the side opposite to the address driver. The decoding circuits all have the same circuit structure. Eight input terminals are connected to either one of the signal lines and are uniformly disposed along the drive signal lines. When the detection circuit monitors the change of either one of the signal lines connected thereto to "0" and detects determination of the input drive signals in the decoding circuit, a control circuit receives an outputted detection signal and changes the enable signal to "0" so as to be brought into a decode-enabled state.

REFERENCES:
patent: 4739497 (1988-04-01), Itoh et al.
patent: 5398206 (1995-03-01), Akizawa et al.
patent: 5659514 (1997-08-01), Hazani
patent: 5699317 (1997-12-01), Sartore et al.
patent: 5721834 (1998-02-01), Milhaupt et al.

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