Address decoder

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S189080, C365S233100

Reexamination Certificate

active

07848173

ABSTRACT:
An address decoder includes N predecoders that receive and logically combine a clock signal and respective address signals to periodically provide respective addresses and complementary addresses. N is an integer greater than one. A first decoder receives the respective addresses and complementary addresses and generates a decoder output based on the received respective addresses and complementary addresses.

REFERENCES:
patent: 4086500 (1978-04-01), Suzuki et al.
patent: 4401903 (1983-08-01), Iizuka
patent: 4488266 (1984-12-01), Spence
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5311479 (1994-05-01), Harada
patent: 5373203 (1994-12-01), Nicholes et al.
patent: 5640108 (1997-06-01), Miller
patent: 6445640 (2002-09-01), Gold
patent: 6677782 (2004-01-01), Kanetani et al.
patent: 2003/0039143 (2003-02-01), Ogane

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