Address decoder

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307279, 307463, 307481, H03K 19096

Patent

active

045815488

ABSTRACT:
An address decoder architecture capable of having a precharge signal for the word line coincident with the enabling of the decoder section to reduce the operating cycle. The word line latch is separate and distinct from the word line driver such that disablement of the word line driver during readdressing of the enabled decoder will not effect the portion of the cycle that the word line maintains its logic state.

REFERENCES:
patent: 4086500 (1978-04-01), Suzuki et al.
patent: 4216389 (1980-08-01), Carter
patent: 4275312 (1981-06-01), Saitou et al.
patent: 4281399 (1981-07-01), Yamamoto
patent: 4289982 (1981-09-01), Smith
patent: 4305139 (1981-12-01), Zbrozek

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