Address decode system

Details Address decode system Address decode system

1980-05-29

1983-11-29

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300, H03K 1300

Patent

active

044183976

ABSTRACT:
An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.

REFERENCES:
patent: 3916169 (1975-10-01), Cochran
patent: 3959774 (1976-05-01), Mead
patent: 4024505 (1977-05-01), Sperling
patent: 4249240 (1981-02-01), Barnich

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