Address converter semiconductor device and semiconductor...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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C365S230090, C365S233100

Reexamination Certificate

active

11501905

ABSTRACT:
An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

REFERENCES:
patent: 5608682 (1997-03-01), Jinbo et al.
patent: 6121815 (2000-09-01), Terada et al.
patent: 11-260068 (1999-09-01), None
patent: 2003-249087 (2003-09-01), None
patent: 2004-070461 (2004-03-01), None
patent: 1998-0005003 (1998-03-01), None

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