Address converter

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Patent

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Details

G06F 500, G06F 1300

Patent

active

042053900

ABSTRACT:
An address converter for decoding a multi-bit binary address has a binary adder to provide a logic subtraction of binary bit information introduced by a plurality of manually settable switches from a predetermined number of most significant binary bits in an address signal, an address-decode circuit for receiving an output signal from the adder and the next order of magnitude of the binary bits in the address signal and a plurality of system subunits which receive an output signal from the address-decode circuit and the remaining least significant bit information in the address signal to access the subunits according to the address signal and the switch settings in a predetermined order.

REFERENCES:
patent: 3818459 (1974-06-01), Vrablik

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