Address/control signal input circuit for a cache controller whic

Details Address/control signal input circuit for a cache controller whic Address/control signal input circuit for a cache controller whic

1991-01-09

1993-01-12

Anderson, Lawrence E.

Boots, shoes, and leggings

36424341, 3642384, 3642596, 3642457, 364DIG1, G06F 1314

Patent

active

051796783

ABSTRACT:
A cache controller is coupled to a cache memory coupled through a bus to a microprocessor, for controlling the cache memory in response to a signal from the microprocessor. The cache controller comprises an address signal terminal and a control signal terminal for receiving an address signal and a control signal from the microprocessor, and a clamp signal terminal for receiving a clamp signal from the microprocessor. The cache controller also includes an input circuit coupled to the address signal terminal, the control signal terminal and the clamp signal terminal for outputting the address signal and the control signal as they are when the clamp signal is inactive and for generating an output address signal and an ouput control signal having a predetermined logic level when the clamp signal is active.

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