Address control circuit for data memory employed in signal delay

Details Address control circuit for data memory employed in signal delay Address control circuit for data memory employed in signal delay

1989-10-20

1991-10-15

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

365194, 36523008, G11C 800, G11C 700

Patent

active

050580760

ABSTRACT:
An address control circuit for a data memory includes a first register for temporarily storing address information applied thereto and for supplying the stored address information to the data memory, a second register for temporarily storing write address information, a third register for temporarily storing offset address information, a write address control circuit coupled to the first and second registers for supplying to the first register address information relative to the write address information and for updating the content of the second register in a data write operation, and a read address control circuit coupled to the first to third registers for producing read address information corresponding to a difference between the content of the second register and the offset address information and for supplying the read address information to the first register in a data read operation.

REFERENCES:
patent: 4348754 (1982-09-01), Haynes et al.
patent: 4549283 (1985-12-01), McDermott, III
patent: 4630301 (1986-12-01), Hohl et al.
patent: 4663741 (1987-05-01), Reinschmidt et al.
patent: 4730272 (1988-03-01), Sullivan
patent: 4740923 (1988-04-01), Kaneko et al.

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