Address control circuit for a video memory of a multi-image disp

Details Address control circuit for a video memory of a multi-image disp Address control circuit for a video memory of a multi-image disp

1989-03-30

1991-06-04

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 22, 358183, H04N 514

Patent

active

050218832

ABSTRACT:
An address control circuit for a video memory of a multi-image display system. The circuit includes a video signal source, a video memory for storing the video signal, an address holding circuit for controlling write addresses of the video memory which outputs address values during a video image period and holds address value corresponding to a start instance of a blanking period during the blanking period and a bias generating circuit for positioning address areas of the video memory in which the video signal is stored.

REFERENCES:
patent: 4570181 (1986-02-01), Yamamura
patent: 4729028 (1988-03-01), Micic et al.
patent: 4746980 (1988-05-01), Petersen
patent: 4748504 (1988-05-01), Ikeda et al.
patent: 4862269 (1989-08-01), Sonoda et al.

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