Address control apparatus of semiconductor memory device...

Details Address control apparatus of semiconductor memory device... Address control apparatus of semiconductor memory device...

2002-05-20

2003-10-21

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Multiplexing

C365S230060

Reexamination Certificate

active

06636452

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to an address control apparatus for a semiconductor memory device using a bank address, and more specifically to an address control apparatus which can be applied to various DRAM macro sets more than 2M~64M, as well as reducing the time required for designing the macro sets.
BACKGROUND OF THE INVENTION
In general, address buffers in a DRAM device perform to receive address signals. Each address signal(e.g., A
0
through An) is independently assigned to one address buffer and one address bus line. And, each address signal provided through each address buffer is stored in an address register in synchronization with an internal clock.
Meanwhile, it is generally known in the address buffers that the address signals are inputted thereto synchronously with row active, read, or write commands. In cases where the address signals are performing a multiplexing operation, the address signals may be used for a row address or a column address in accordance with the kinds of commands. In cases without the multiplex procedure, i.e., de-multiplexing, the address signals are classified into row and column address signals at the time they are incoming, and then provided to the address buffers in response to activation of row and column signals. At this time, the row and column address signals are converted into pre-decoded signals by row and column pre-decoders, respectively.
FIG. 1
is a block diagram of the conventional demultiplexing address control apparatus for receiving the row and column address signals which are separately input thereto.
Referring to
FIG. 1
, the conventional address control unit includes a row address buffer
10
, a column address buffer
30
, and a bank address buffer
50
, theses three buffers being associated with their own signal input paths.
First, the row address buffer
10
receives and buffers external row address signals RAN<0:10>, and then generates internal row address signals RA<0:10> and /RA<0:10>. The internal row address signals RA<0:10> and /RA<0:10> are applied to a row pre-decoder
20
and converted into pre-decoded row address signals. At that time, first refresh control unit
15
applies control signals RCNT<0:10> and /RCNT<0:10> to the row pre-decoder
20
in response to clock signal CLK in order to control a refresh operation.
The column address buffer
30
receives and buffers external column address signals CAN<0:4>, and then generates internal column address signals CA<0:4> and /CA<0:4>. The internal column address signals CA<0:4> and /CA<0:4> are applied to a column decoder
40
and converted into decoded column address signals.
The bank address buffer
50
receives and buffers external bank address signals BAN<0:1>, and then generates internal bank address signals BA<0:1> and /BA<0:1>. The internal bank address signals BA<0:1> and /BA<0:1> are applied to a bank control unit
60
. Here, the bank address signals serve to activate a selected bank in multi-bank DRAM.
However, according to the conventional address control apparatus, since the row address buffer
10
, the column address buffer
30
, and the bank address buffer
50
respectively should have their own signal input paths to buffer the address signals, a time required for designing a DRAM macro set inevitably increases. Such a long time for design makes it difficult to completely fabricate the DRAM macro set in a given turn-around-time (TAT).
As a result, it would be difficult to design DRAM macro sets having various memory densities of 2M through 64M because of the numerous signal paths for the buffers.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to utilize a bank address as a row address in accordance with a bank architecture.
In order to attain the above object, according to an aspect of the present invention, it is an object of the present invention to provide an address control apparatus for a semiconductor memory device using a bank address, the address control unit including a row address buffer for buffering and generating a row address signal, a bank address buffer for buffering and generating a bank address signal, a bank control unit for activating a bank selected in response to the buffered bank address signal provided from the bank address buffer, an address control unit for converting the buffered bank address signal provided from the bank address buffer into an additional row address signal, and then generating, and a row pre-decoder for pre-decoding the buffered row address signal provided from the row address buffer and the additional row address signal converted in the address control unit, and then generating a composite address signal.


REFERENCES:
patent: 4195238 (1980-03-01), Sato
patent: 4451908 (1984-05-01), Takemae et al.
patent: 5546352 (1996-08-01), Sato et al.
patent: 5761694 (1998-06-01), Rao
patent: 5815460 (1998-09-01), Watanabe
patent: 6166988 (2000-12-01), Ryu et al.
patent: 6262923 (2001-07-01), Fujita

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