Address change detecting system for a memory

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36518905, 307480, G11C 800, H03K 19017

Patent

active

053574800

ABSTRACT:
An address change detection system detects a change in an address input in a memory to initiate a read or write operation. The address change detection system uses a transition detection delay unit for each address bit of the memory. The transition detection delay unit is responsive to a change in an associated address bit to provide a clock output pulse of predetermined duration. The transition detection delay unit comprises a latch which is coupled to the associated address bit, and a pair of Delay Ring Segment Buffers, each coupled to a respective output of the latch. The output of the Delay Ring Segment Buffer is provided to cascaded NAND gates to form the output of the transition detection delay unit. The outputs of all of the transition detection delay units are provided to an OR gate, the output of which provides an indication of an address change. The address change detection circuit can also be used to detect a change in at least one of a plurality of binary valued inputs for applications other than memory systems.

REFERENCES:
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patent: 4922122 (1990-05-01), Dubujet
patent: 4982117 (1991-01-01), Matsuzaki et al.
patent: 5003513 (1991-03-01), Porter et al.
patent: 5030853 (1991-07-01), Vinal
patent: 5198708 (1993-03-01), Gillingham

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