Boots – shoes – and leggings
Patent
1991-06-04
1992-09-15
Fleming, Michael R.
Boots, shoes, and leggings
364DIG1, 364240, 3642403, 3642456, 364247, 3642422, 3642549, 3642551, 3642554, G06F 1200
Patent
active
051485397
ABSTRACT:
An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.
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British Search Report from British Application No. 8824168.2.
Amako Norihisa
Enomoto Hiromichi
Jikihara Masami
Kobayashi Kazushi
Fleming Michael R.
Hitachi , Ltd.
Sheikh Ayaz R.
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