Address bus arbiter for pipelined transactions on a split bus

Details Address bus arbiter for pipelined transactions on a split bus Address bus arbiter for pipelined transactions on a split bus

1997-05-20

1998-09-29

Sheikh, Ayaz R.

G06F 13362

Patent

active

058156763

ABSTRACT:
An address bus arbiter is implemented using a state machine. A first through third states of the state machine grant the address bus to a respective first through third bus masters, each having a different priority associated therewith. Idle states are interposed between states. The idle state may be reached from one the bus grant states when a cache controller initiates a tag invalidation cycle or a cache allocation cycle. The idle state may also be reached when a first bus master commences a transaction cycle with a second bus master.

REFERENCES:
patent: 4473880 (1984-09-01), Budde et al.
patent: 4547845 (1985-10-01), Ross
patent: 4682284 (1987-07-01), Schrofer
patent: 4817037 (1989-03-01), Hoffman et al.
patent: 4896256 (1990-01-01), Roberts
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5073851 (1991-12-01), Masterson et al.
patent: 5119495 (1992-06-01), King
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5191649 (1993-03-01), Cadambi et al.
patent: 5226150 (1993-07-01), Callander et al.
patent: 5237567 (1993-08-01), Nay et al.
patent: 5289585 (1994-02-01), Kock et al.
patent: 5299315 (1994-03-01), Chin et al.
patent: 5319766 (1994-06-01), Thaller et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5339399 (1994-08-01), Lee et al.
patent: 5347648 (1994-09-01), Stamm et al.
patent: 5353429 (1994-10-01), Fitch
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5363485 (1994-11-01), Nguyen et al.
patent: 5367678 (1994-11-01), Lee et al.
patent: 5375215 (1994-12-01), Hanawa et al.
patent: 5377324 (1994-12-01), Kabemoto et al.
patent: 5398244 (1995-03-01), Matthews et al.
patent: 5416910 (1995-05-01), Moyer et al.
patent: 5440751 (1995-08-01), Santeler et al.
patent: 5450555 (1995-09-01), Brown, III et al.
patent: 5473762 (1995-12-01), Krein et al.
patent: 5485586 (1996-01-01), Brash et al.
patent: 5488709 (1996-01-01), Chan
PowerPC.TM. 601, RISC Microprocessor User's Manual, Motorola Inc. 1993, pp. 6-16-6-17, 9-1-9-12; and 9-18-9-19.
IBM Technical Disclosure Bulletin, "Local Main Store Bus With Separately Controlled Command and Data Portions", vol. 36, No. 11, Nov. 1993, pp. 419-420.
IBM Technical Disclosure Bulletin, "Separating The Interaction Of Address And Data State During Bus Data Transfers", vol. 37, No. 5, May 1994, New York, USA, pp. 337-338.
IBM Technical Disclosure Bulletin, "Peripheral Component Interconnect Target/60X Snoop Cycle", vol. 38, No. 3, Mar. 1995, pp. 469-471.

Affiliated with

Also associated with

Rating

Address bus arbiter for pipelined transactions on a split bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address bus arbiter for pipelined transactions on a split bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address bus arbiter for pipelined transactions on a split bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-695343