Address buffer with ATD generation

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307446, 307455, 3652335, H03K 19096, H03K 1908, H03K 19086, G11C 800

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active

053131207

ABSTRACT:
An address buffer (20) provides an ATD pulse in response to an address signal transitioning from one logic state to another. The address buffer (20) includes a differential amplifier (22), an emitter-follower transistor (35), and two P-channel transistors (36 and 37). A first current electrode of each of the P-channel transistors is connected to the output nodes (101 and 102) of the differential amplifier (22), and a second current electrode of each of the P-channel transistors (36 and 37) is connected to the base of the emitter-follower transistor (35). Delayed control signals are provided to the gates of the P-channel transistors (36 and 37) by a level converter circuit (60) to cause an ATD pulse to be provided at the emitter of the emitter-follower transistor (35). Generating the ATD pulse in the address buffer allows the ATD pulse to be produced very quickly.

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Takashi Akioka et al., "A 6-ns 256-kb BiCMOS TTL SRAM", IEEE Jounral of Solid-State Circuits, Mar. 1991, vol. 26, No. 3, Fig. 8, p. 442.

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