Address buffer having (N/2) stages

Details Address buffer having (N/2) stages Address buffer having (N/2) stages

2005-07-05

2005-07-05

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233100

Reexamination Certificate

active

06914850

ABSTRACT:
An address buffer only having (N/2) stages, capable of performing the same function as that of an N-stage address buffer is provided. The address buffer used in a semiconductor device having N (where N is a natural number) additive latency comprises (N/2) serially-connected flip-flops, and an address control circuit which generates an address enable signal in response to a clock signal and a command signal. Each of the (N/2) flip-flops is clocked to the address enable signal and sequentially latches an external address.

REFERENCES:
patent: 5269012 (1993-12-01), Nakajima
patent: 6711084 (2004-03-01), Ishida et al.

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