Address buffer for high speed static random-access-memory device

Details Address buffer for high speed static random-access-memory device Address buffer for high speed static random-access-memory device

1996-04-09

1997-11-25

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, G11C 800

Patent

active

056919530

ABSTRACT:
An address buffer for high speed static random-access-memory (SRAM) devices is disclosed. The address buffer includes a buffer stage, an out-phase variable buffer circuit and an in-phase variable buffer circuit. The buffer stage includes a number of series-connected buffer units for transmitting an input address signal. The out-phase variable buffer circuit is connected to the buffer stage for providing a first buffer condition in a write period and for providing a second buffer condition in a read period. The in-phase variable buffer circuit is also connected to the buffer stage for providing a third buffer condition in the write period and for providing a fourth buffer condition in the read period. An external address signal can be delayed by the various buffer conditions of the address buffer during the write period to optimize the operation of the SRAM devices, and the various buffer conditions will not affect the read period.

REFERENCES:
patent: 4707809 (1987-11-01), Ando
patent: 4825420 (1989-04-01), Min

Affiliated with

Also associated with

Rating

Address buffer for high speed static random-access-memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address buffer for high speed static random-access-memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address buffer for high speed static random-access-memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2112978