Address buffer for blocking noise

Details Address buffer for blocking noise Address buffer for blocking noise

1995-12-18

1997-05-27

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365233, 3652335, 36523001, H03K 1716, G11C 700

Patent

active

056338333

ABSTRACT:
An address buffer capable of preventing malfunctions of a memory device or preventing delay of the signal outputted from the output buffer by blocking noise, which inverts or blocks the signal outputted from the address signal input unit according to a PMOS control signal and an NMOS control signal, and latches the signal outputted from the clock inverter in the latch unit. The PMOS and the NMOS control signals are outputted to the clock inverter by logically operating the control signal outputted from the control signal generating unit according to the output signal of the latch unit, thereby blocking a noise generated in the address input unit by the signal outputted from the output buffer by the clock inverter.

REFERENCES:
patent: 4451745 (1984-05-01), Itoh et al.
patent: 5450019 (1995-09-01), McClure et al.
patent: 5459693 (1995-10-01), Komarek et al.

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