Address buffer for a MOS-memory module

Details Address buffer for a MOS-memory module Address buffer for a MOS-memory module

1979-08-15

1981-08-18

Dixon, Harold A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307DIG1, 307260, H03K 500

Patent

active

042849101

ABSTRACT:
An address buffer is disclosed in MOS technology with an address memory circuit exhibiting an address input driven via a transfer signal and having two complementary address outputs and two complementary signal outputs of high signal level. An isolating amplifier is provided with a following-connected output stage. The isolating amplifier is driven via a control clock pulse and supplies complementary control signals. It also has two parallel paths each consisting of the driven segments of two transistors. These parallel paths are connected to the drive clock pulse at a first common node and are connected to a base voltage source at a second common node. The first transistor of each parallel path is driven via a respective high signal level signal output of the address memory circuit and the second transistor of each parallel path is driven via a respective address output of the address memory circuit which is inverse to the high level signal output.

REFERENCES:
patent: 4077031 (1978-02-01), Kitagawa et al.
patent: 4087704 (1978-05-01), Mehta et al.
patent: 4214175 (1980-07-01), Chan

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