Address buffer circuit with low power consumption

Details Address buffer circuit with low power consumption Address buffer circuit with low power consumption

1980-12-08

1984-05-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307583, 307270, H03K 19092, H03K 17687

Patent

active

044517459

ABSTRACT:
In a latch-type address buffer circuit for use in a clock-synchronous CMIS.RAM, a transistor is connected between an inverter, which is supplied with an address signal and the power source. A clock circuit is provided for generating an internal clock signal by which only in the period of latching the input address signal, the transistor is turned ON to make the inverter operative, thus reducing the total power consumption.

REFERENCES:
patent: 3859637 (1975-01-01), Platt et al.
patent: 4074148 (1978-02-01), Sato
patent: 4124806 (1978-11-01), Rusznyak
patent: 4146802 (1979-03-01), Moench
patent: 4288706 (1981-09-01), Reese et al.
patent: 4344003 (1982-08-01), Harmon et al.

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