Address buffer circuit in semiconductor memory

Details Address buffer circuit in semiconductor memory Address buffer circuit in semiconductor memory

1976-06-03

1978-02-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307270, 307DIG1, 365205, H03K 3286, H03K 3353

Patent

active

040741486

ABSTRACT:
In an address buffer circuit in a semiconductor memory including a flip-flop formed of MISFETs and an output circuit consisting of two drivers each formed of MISFETs, and producing a binary address signal, the flip-flop is supplied with a constant operating voltage and triggered by a pulse signal of shorter pulse width than that of a chip enable signal and the MISFETs of the driver on the ground side have the gates cross-coupled to the outputs of the respective drivers so that at least one grounding MISFET in each driver is turned on in the outputting period to prevent the floating of the output level.

REFERENCES:
patent: 3848237 (1974-11-01), Geilhufe et al.
patent: 3868657 (1975-02-01), Hoffman et al.
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3906464 (1975-09-01), Lattin
patent: 3938109 (1976-02-01), Gionis et al.
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3969706 (1976-07-01), Proebsting et al.

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