Address buffer circuit for memory device

Details Address buffer circuit for memory device Address buffer circuit for memory device

2006-06-13

2006-06-13

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S193000, C365S203000, C365S230030

Reexamination Certificate

active

07061824

ABSTRACT:
Disclosed is an address buffer circuit for a memory device, the address buffer circuit comprising: a first address input buffer group and a second address input buffer group for receiving an address signal applied from the exterior; and a control unit for controlling operation of the second address input buffer group. Herein, operation of the first address input buffer group is controlled by a first control signal, and the control unit receives a second control signal enabled when all banks of the memory device enter an active state and controls operation of the second address input buffer group.

REFERENCES:
patent: 5450341 (1995-09-01), Sawada et al.
patent: 5504710 (1996-04-01), Somon
patent: 6256260 (2001-07-01), Shim et al.
patent: 6704242 (2004-03-01), Kobayashi
patent: 2005/0174827 (2005-08-01), Yeh

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