Address buffer circuit for high speed semiconductor memory

Details Address buffer circuit for high speed semiconductor memory Address buffer circuit for high speed semiconductor memory

1976-12-09

1978-08-29

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307362, 307DIG1, 307DIG4, 307DIG5, 365230, H03K 3286, H03K 3353, G11C 800

Patent

active

041106393

ABSTRACT:
A high speed address buffer circuit for use in MOS/LSI semiconductor memories or the like. An unbalanced, dynamic cross-coupled pair of MOS driver transistors is used to sense an address input during a short time window, and internal address signals are generated from the state of the sense circuit. Sensing nodes are precharged and equalized prior to the time window, and the node which is to stay at the logic "1" level is held at a high level by boosting capacitors to which a delayed clock signal is applied. The state of the sense circuit is sampled at a time after the delayed clock and high level addresses are generated.

REFERENCES:
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 3848237 (1974-11-01), Geilhufe
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3906464 (1975-09-01), Lattin
patent: 3959781 (1976-05-01), Mehta et al.
patent: 4010453 (1977-03-01), Lewis
patent: 4028557 (1977-06-01), Wilson
patent: 4031415 (1977-06-01), Redwine et al.
patent: 4038567 (1977-07-01), Lewis et al.
Kuo et al., "16-K RAM Built With Proven Process May Offer High Start-up Reliability"; Electronics (pub.); pp. 81-86; 5/13/76.
Bishop et al., "High-Sensitivity, High Speed FET Sense Latch"; IBM Tech. Discl. Bull.; vol. 18, No. 4, pp. 1021-1022; 9/1975.

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