Address buffer circuit

Details Address buffer circuit Address buffer circuit

1980-07-23

1982-07-27

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365201, G11C 800

Patent

active

043421032

ABSTRACT:
An address buffer circuit is used in a memory device, for example in an EPROM device, and enables high speed testing of the memory device. The address buffer circuit can output "1" or "0" from both a positive output terminal and a negative output terminal when an input word address signal having a signal level different from the usual signal level is applied to an input of the address buffer circuit, so that a plurality of word lines can be selected at a time.

REFERENCES:
patent: 4074148 (1978-02-01), Sato
patent: 4104733 (1978-08-01), Satoh
patent: 4110639 (1978-08-01), Redwine

Affiliated with

Also associated with

Rating

Address buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2027905