Address buffer and method for buffering address in...

Details Address buffer and method for buffering address in... Address buffer and method for buffering address in...

2006-12-19

2008-11-11

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233500

Reexamination Certificate

active

07450463

ABSTRACT:
An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch input address and a clock. A synchronous address latch unit generates a synchronous output address from a command pulse signal and the second latch input address. A synchronous mode detecting unit determines whether a mode is a synchronous mode or not from a valid address signal and the clock to generate a synchronous mode signal. An asynchronous address latch unit generates an asynchronous output address from the synchronous mode signal, an address strobing signal, and the second latch input address.

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