Address buffer

Details Address buffer Address buffer

1993-04-30

1994-08-16

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365201, G11C 800

Patent

active

053392779

ABSTRACT:
An address buffer which allows for the simultaneous selection and/or deselection of a plurality of rows and/or columns within a memory array. A first and a second circuit generate a true and a complementary signal, respectively, during normal operations of the integrated circuit. When desired, the first and second circuits may be used to generate two signals of the same voltage level. The two signals of the same voltage level may then be used by an address decoder to simultaneously select and/or deselect a plurality of rows and/or columns within a memory array.

REFERENCES:
patent: 4651304 (1987-03-01), Takata
patent: 5208776 (1993-05-01), Nosu et al.

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