Address arithmetic circuit of a memory unit utilized in a proces

Details Address arithmetic circuit of a memory unit utilized in a proces Address arithmetic circuit of a memory unit utilized in a proces

1983-07-26

1986-06-10

Thomas, James D.

Boots, shoes, and leggings

381 31, 381 41, G06F 1200, G10L 302

Patent

active

045946876

ABSTRACT:
A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc. The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits. The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder. The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder. The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing. According to the type of processing algorithms and corresponding addressing modes, the arithmetic circuit performs the resetting or incrementing of the two counters, controlling the selection operation of the two selection circuits, controlling the number of shifts of the shift circuit, and resetting the third register.

REFERENCES:
patent: 3591784 (1971-07-01), Cutter
patent: 3662115 (1972-05-01), Saito
patent: 3748451 (1973-07-01), Ingwersen
patent: 3875391 (1975-04-01), Shapiro
patent: 4181976 (1980-01-01), Collins
patent: 4393468 (1983-07-01), New
A A. C. D. de Figueivedo paper entitled "High-Speed Technique for Digital Signal Processing", Proceeding of 1979 ISCAS, pp. 977 and 978.
A Richard Klahn et al paper entitled "The Time-Saver: FFT Hardware", Electronics, Jun. 24, 1968, pp. 92-97.
Fumitada Itakura et al, paper entitled "A Hardware Implementation of a New Narrow to Medium Band Speech Coding", I.E.E.E. International Conference on Acoustics, Speech and Signal Proceeding, 1982, May, pp. 1964-1967.
A Wen-Hsiung Chen et al paper entitled "A Fast Computational Algorither for the Discrete Cosine Transform", I.E.E.E. Transactions on Communications, vol. COM-25, No. 9, Sep. 1977, pp. 1004-1009.
A James L. Flanagan et al paper entitled "Speech Coding", I.E.E.E. Transaction on Communications, vol. COM-27, No. 4, Apr. 1979, pp. 710 through 737.
A paper of Masaki Honda et al of the title "Adaptive Bit Allocation Scheme in Predictive Coding of Speech", I.E.E.E. International Conference on Acoustics, Speech and Signal Processing, May 1982, pp. 1672 through 1675.
A paper of Raine Zelinski et al, I.E.E.E. Transaction on Acoustics, Speech and Signal Processing, vol. ASSD-25, No. 4, Aug. 1977, pp. 299-309.

Affiliated with

Also associated with

Rating

Address arithmetic circuit of a memory unit utilized in a proces does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address arithmetic circuit of a memory unit utilized in a proces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address arithmetic circuit of a memory unit utilized in a proces will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2408661