Address and data interface unit

Details Address and data interface unit Address and data interface unit

1980-04-14

1982-11-23

Thomas, James D.

Boots, shoes, and leggings

G06F 930

Patent

active

043608914

ABSTRACT:
A large scale integrated circuit is designed to handle bus-to-bus data and address transfers, manipulation, and temporary storage. A key feature of the device is that it generates error correcting code parity bits on a byte wide basis so that ECC check bits for a multi-byte word can be generated externally with a minimum of hardware, and includes circuitry responsive to an error syndrome for correcting a single error within a byte. Data manipulation capabilities include standard logical operations, single bit shift operations, binary 2's complement arithmetic addition and subtraction, and decimal addition and subtraction. In addition, an input data byte on any bus can be passed unaltered or inverted to any other bus. The device is capable of receiving operands from one or two of three bidirectional data buses, performing a desired arithmetic or logical operation on the operand or operands, and returning the result to any one of the bidirectional buses including one which may have supplied one of the operands. An instruction is decoded at the leading edge of a clock pulse, and executed during the clock pulse. The result is entered into a result register on the trailing edge of the clock pulse so that that result is available to any bus during the same microcycle the instruction and operands are received.

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