Address and data bus arbiter for pipelined transactions on a spl

Details Address and data bus arbiter for pipelined transactions on a spl Address and data bus arbiter for pipelined transactions on a spl

1995-04-28

1999-05-04

Sheikh, Ayaz R.

395729, G06F 13362

Patent

active

059012951

ABSTRACT:
An arbiter employs both an address bus arbiter and a data bus arbiter for supporting pipelined, split bus transactions. The address arbiter may be implemented using a state machine. A first through third states of the state machine grant the address bus to a respective first through third bus masters, each having a different priority associated therewith. Idle states are interposed between states. The data bus arbiter may be implemented using a circular FIFO having a plurality of pointers to keep track of present and future bus masters using the data bus.

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