Address alignment system for semiconductor memory device

Details Address alignment system for semiconductor memory device Address alignment system for semiconductor memory device

1997-06-06

1999-02-23

Nelms, David

Static information storage and retrieval

Addressing

395425, G11C 800

Patent

active

058751475

ABSTRACT:
An address alignment system for a semiconductor memory device includes a plurality of address decoders for decoding a received address, dividing m cells of n bit size into at least two blocks, and individually accessing the cells on the block basis; a controlling circuit for producing data input/output selection signals according to the received address; a plurality of cell selectors connected to cells on the same row of the blocks for selecting cells in any one block in response to the data input/output selection signals produced by the controlling circuit; a plurality of input/output selectors for selecting one of the cell selectors to re-align data in the order of addresses according to the data input/output selection signals produced by the controlling circuit; and a plurality of input/output ports each connected to one of the input/output selectors.

REFERENCES:
patent: 5138705 (1992-08-01), Lo et al.
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5367495 (1994-11-01), Ishikawa
patent: 5561784 (1996-10-01), Chen et al.
patent: 5634038 (1997-05-01), Saitoh
Intel 80960CA Product Overview (Sep. 1989), pp. 3-187.

Affiliated with

Also associated with

Rating

Address alignment system for semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address alignment system for semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address alignment system for semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-312862