Address administration unit of a multi-processor central control

Details Address administration unit of a multi-processor central control Address administration unit of a multi-processor central control

1987-09-25

1989-10-10

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

34082507, 364200, H04Q 300

Patent

active

048735213

ABSTRACT:
An address management unit is provided for the conversion of logical addresses contained in a program into physical addresses for a multi-processor central control unit of a computer-controlled communications switching system comprising a central bulk storage, and additional memories in the processors, and peripheral units, a logical address forms a polysyllable address word of which one address syllable corresponds to the logical starting address of a logical address space and the other address syllable corresponds to the logical address within this logical address space. A special-purpose memory serves the purpose of storing four-syllable words having a long word length which are respectively stored therein under the addresses formed by the one address syllables. The four word syllables each correspond to a specific control signal in which the first word syllable corresponds to the address of the physical address space, the second syllable corresponds to the plurality of physically-present addresses of the physical address space to be selected, the third syllable corresponds to the total physical object to be selected, and the fourth syllable corresponds to respective information concerning access rights, whereby the fourth syllable monitors the access to the unit to be selected in accordance with the third word syllable.

REFERENCES:
patent: 4145745 (1979-03-01), De Bijl et al.
patent: 4163280 (1979-07-01), Mori et al.
patent: 4466056 (1984-08-01), Tanahashi
Hu et al., "Memory-Management Units Help 16 Bit .mu.Ps to Handle Large Memory Systems", Electronic Design, vol. 28, Apr. 1980, pp. 128-135.
Intel, Advance Inform 80386 High Performance Microprocessor with Integrated Memory Management, 10-85, Order No. 231631-001, 10/85.
Electrical Engineering, "Memory Management with the M68000 Family", Mar. 1985, pp. 47-49.
Klaus Schreier, "High Throughout Processing Scheme in Digital Communications", International Zurich Seminar on Digital Communications, Mar. 1986, pp. 213-218.

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