Address access path control circuit

Details Address access path control circuit Address access path control circuit

1996-08-30

1998-09-08

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523008, 365201, 3652335, G11C 800, G11C 700

Patent

active

058055223

ABSTRACT:
An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.

REFERENCES:
patent: 4384347 (1983-05-01), Nakano
patent: 4855957 (1989-08-01), Nogami
patent: 5280456 (1994-01-01), Okajima et al.
patent: 5289431 (1994-02-01), Konishi
patent: 5444305 (1995-08-01), Matsui
patent: 5502675 (1996-03-01), Kohno et al.

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