Horology: time measuring systems or devices – Time interval – Electrical or electromechanical
Reexamination Certificate
1999-05-28
2002-03-12
Miska, Vit (Department: 2859)
Horology: time measuring systems or devices
Time interval
Electrical or electromechanical
C324S073100
Reexamination Certificate
active
06356513
ABSTRACT:
DESCRIPTION
The present invention concerns a dummy cell test circuit for measuring delay times in embedded circuits, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path.
A circuit having no direct access, also known as ‘embedded’ circuit, is a circuit, in particular a semiconductor memory located on an integrated chip, whose configuration is arranged so as to be surrounded by further circuitry; in such a situation, said embedded circuit has no direct access from any inputs and outputs of the integrated chip without passing through said further circuitry.
In order to test embedded circuits, in particular memory arrays as referred to later for simplicity's sake, it is known to have test chips so modified to allow their testing, which have input and output pads of the circuits to be tested equipped with buffer circuits, and said pads are accessible from outside by suitable pads for use with the so-called ‘probe-cards’ of the integrated circuit test machines. Thus, memory test operation will be easier, but the ad-hoc introduced buffer circuits generate signal propagation delays, causing a serious hindrance for determining the real propagation times of the memory under test. EBT (Electron Beam Test) test machines are known, which use electronic beams to stimulate signals in the interconnects and measure delays. However, said EBT test machines are extremely complex and expensive.
In order to solve this drawback in a more cost-effective way it is known to use dummy cell test circuits.
FIG. 1
shows a partial diagram of an integrated circuit
1
, comprising a memory
2
, which has a clock input ICK and an output Q.
The clock input ICK is connected upstream through an input buffer circuit A
1
to an input pad IN
1
, which is apt to receive a clock signal CK. In reality, the buffer circuit A
1
is representative of a buffer cascade.
A selection block
3
is then provided downstream the memory
2
, which may be obtained for distance through a multiplexer circuit.
Output Q of the memory
2
is selected through an external selection signal SEL injected on a selection pad SP and available on an external output pad OUT through an output buffer circuit B, which also consists of a buffer or inverters cascade.
The path of the clock signal CK from the input pad IN
1
to the output pad OUT forms a main path P
1
, which is considered to determine the memory propagation delays referred to the active edge of the clock signal CK.
However, since also the input buffer circuit A
1
, the selection block
3
and the output buffer circuit B belong to the main path P
1
, said circuits introduce additional delays with respect to those introduced by the memory
2
between the input ICK and output Q. Since the measurement takes place between the input pad IN
1
and output pad OUT, so that dummy delays are summed to memory delays, a second input pad IN
2
is provided followed by an input buffer circuit A
2
repeating the input buffer circuit A
1
and connected to the selection block
3
, so as to obtain a dummy path P
2
further comprising the output buffer circuit B and output pad OUT. The dummy path P
2
in conjunction with the selection pad SP forms a test circuit
4
. Selecting the dummy path P
2
through the selection signal SEL, propagation time values now detected on the output pad OUT are used to subtract them from the values measured for the main path P
1
and obtain as a final result the real delay introduced by the memory between the input ICK and output Q.
However, the test circuit
4
represented in
FIG. 1
has several drawbacks, since in the practice it is extremely difficult to obtain a dummy path P
2
mirroring the main path P
1
, particularly due to difficulties in obtaining circuitry interconnects. As a result, capacitive loads distributed along the circuitry interconnects are different ones, the same as their deriving propagation delays. Therefore, the difference of propagation times measured on the main path P
1
and dummy path P
2
do not supply a proper safe propagation times value of the memory under test.
Moreover, sizing of input buffer circuits is particularly difficult, since not only it should be tried to obtain circuits introducing the same capacity effects, but at the same time it must also be attempted to obtain circuits with a driving capacity suitable for driving the capacities available downstream, which are also different, as mentioned above. As a result, such a number of project variables makes it extremely difficult to obtain an efficient sizing of the input circuits and correct evaluation of delays times.
According to the American patent U.S. Pat. No. 4,878,209, a pulse signal is sent to an input for selecting memory operational modes and transmit a test signal to a further test input. Said signals operate on output buffers at the memory and on a proper test buffer. In particular, two outputs are available, one for the data from the memory and the other for the output test signal; using the test signal for enabling the memory output will operate the circuit allowing an exact measurement of the propagation delay.
The solution described in the above patent has a rather complex actuation, since it requires sending a special test signal as well as a complicated timing control of the signals inside the chip. In this instance, both the dummy path and main path as defined with reference to
FIG. 1
will interact and require complex test machines for a result. Furthermore, only the slower memory output can be measured, i.e. not all memory outputs.
It is the object of the present invention to solve the above drawbacks and provide a dummy cell test circuit for measuring delay times in embedded circuits, having a more efficient and improved performance.
In this frame, it is the main object of the present invention to provide a dummy cell test circuit for measuring delay times in embedded circuits, which is not subject to capacity differences with respect to the main path.
A further object of the present invention is to provide a dummy cell test circuit for measuring delay times in embedded circuits, which simplifies input buffer circuits design.
A further object of the present invention is to provide a dummy cell test circuit for measuring delay times in embedded circuits, resulting in a low circuitry complexity and cost-effective manufacture.
A further object of the present invention is to provide a dummy cell test circuit for measuring delay times in embedded circuits, which does not require additional input pads nor external selection signals.
A further object of the present invention is to provide a dummy cell test circuit for measuring delay times in embedded circuits, which makes all embedded circuit outputs accessible for test operations.
In order to achieve such aims, it is the object of the present invention to provide a dummy cell test circuit for measuring delay times in embedded circuits, incorporating the features of the annexed claims, which form an integral part of the description herein.
REFERENCES:
patent: 4866685 (1989-09-01), Lee
patent: 4878209 (1989-10-01), Bassett et al.
patent: 5058087 (1991-10-01), Welzhofer et al.
patent: 5614818 (1997-03-01), El Ayat
Fleit Kain Gibbons Gutman & Bongini P.L.
Miska Vit
STMicroelectronics S.r.l.
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