Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-06-26
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C257S510000
Reexamination Certificate
active
06372605
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor processing, and, more particularly, to forming shallow-trench isolation structures during semiconductor processing.
2. Description of the Related Art
The fabrication of integrated circuits typically involves placing numerous devices on a single semiconductor substrate. Isolation structures are used to electrically isolate one device from another. Isolation structures define field regions of the semiconductor substrate, and the device areas define active regions. Individual devices may then be interconnected by running conducting lines over the isolation structures.
A popular isolation technology used in integrated circuits involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS processing, involves oxidizing field regions between device active regions. The oxide grown in field regions is termed field oxide. Field oxide is grown during the initial stages of integrated circuit fabrication before the gate conductor and source/drain regions are formed in active regions. By growing a thick field oxide in isolating field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS processing has remained a popular isolation technology, there are several inherent problems. First, during fabrication, field oxide can extend beyond the field region to form oxide structures that, in many instances, can encroach unacceptably into the device active regions. Second, the pre-implanted channel-stop dopant often redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active region periphery causing problems known as narrow-width effects. Third, the thickness of field oxide can cause large height disparities across the semiconductor topography between field regions and active regions. Topological disparities can cause planarity problems that can become severe as circuit-critical dimensions shrink. Lastly, field oxide is typically significantly thinner in small field regions (i.e., field regions of small lateral dimension) than in field regions with relatively large lateral dimensions, resulting in undesirable variations in field-oxide thickness for differently sized field regions. Despite advances made to decrease the occurrences of oxide structures encroaching into active regions, channel-stop encroachment, non-planarity, and variable field-oxide thickness, it appears that LOCOS technology is still inadequate for deep sub-micron technologies.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as shallow-trench isolation (STI). The STI process is better suited than LOCOS technology for isolating densely spaced active devices using field regions less than, e.g., 3.0-5.0 microns in the lateral dimension. Narrow-width STI structures may be used to isolate densely spaced devices, and larger width STI structures may be used to isolate devices that are spaced further apart.
The shallow-trench isolation process involves the steps of etching a silicon substrate to a relatively shallow depth, e.g., between 0.2 to 0.5 microns, and then filling the shallow trench with a deposited dielectric. Some STI processes include an interim step of growing oxide on the trench walls prior to filling the trench with the dielectric. The trench dielectric may comprise decomposed tetraethyl-ortho-silicate (“TEOS”) deposited using a high-density plasma chemical vapor deposition (“HDPCVD”) process. The HDPCVD process may, for example, be performed at approximately 400-600° C. in a chamber at either atmospheric or low pressure.
FIGS. 1A-E
show a conventional method of forming shallow-trench isolation structures. In
FIG. 1A
, active regions
142
, comprising a pad oxide
145
and a silicon nitride layer
146
, are formed on a substrate
140
. Using photolithography and etching, the pad oxide
145
, the silicon nitride layer
146
, and a part of the substrate
140
are selectively removed to form shallow trenches
144
between the active regions
142
. In
FIG. 1B
, using an HDPCVD process, an oxide layer
148
is formed over the substrate
140
. Due to the shallow trenches
144
, the oxide layer
148
formed by the HDPCVD process has a profile in which pyramid-like oxide horns are formed on the active regions
142
.
In
FIG. 1C
, a photo-resist layer is formed on the oxide layer
148
. Using photolithography, the photo-resist layer is selectively removed to define a reverse-tone active mask
150
having openings (e.g.,
152
) formed over large (i.e., wide) active regions (e.g.,
142
a
) that expose the oxide layer
148
. Active regions that are narrower than a certain critical dimension (e.g., about 0.9 microns), do not get exposed by the reverse-tone mask. Since only the oxide layer
148
on the central part of the large active regions is exposed through the mask openings, the oxide layer
148
on the shallow trenches
144
is not exposed.
In
FIG. 1D
, the exposed oxide layer
148
within the opening
152
is dry-etched back by an amount roughly equal to the total trench step height (including the pad oxide and silicon nitride layer), and the reverse-tone mask
150
is then stripped (i.e., removed), leaving oxide structures
148
b
on top of the small (i.e., narrow) active regions
142
and oxide structures
148
a
on top of the large active regions
142
a.
In
FIG. 1E
, using chemical-mechanical polishing (CMP), the oxide layer
148
including oxide horns
148
a
and
148
b
are planarized with the silicon nitride layer
146
as an etch stop, so that the remaining oxide regions
148
c
within the shallow trenches
144
have the same level as the silicon nitride regions
146
.
FIG. 1E
shows an idealized result in which CMP processing removes excess, unwanted material from the semiconductor wafer to create a uniform planarized surface.
Prior art shallow-trench isolation techniques, such as that shown in
FIGS. 1A-E
, have certain disadvantages. In prior art STI techniques, the oxide layer (e.g., layer
148
in
FIG. 1B
formed by an HDPCVD process) over the substrate must be thick enough to ensure that there is enough margin during CMP processing to planarize the oxide layer (i.e., remove the oxide horns) before the silicon nitride layer (e.g., layer
146
in
FIG. 1E
) is reached in order to provide uniform polishing of the entire wafer surface. For the prior art, this implies that the HDPCVD oxide layer
148
of FIG. IB must be at least about 1.5-2.0 times the total trench step height (i.e., substrate trench depth plus thicknesses of the pad oxide and silicon nitride layer). For example, for a trench depth of 0.3 microns and a silicon nitride layer thickness of 0.12 microns, a typical HDPCVD oxide layer
148
is about 0.7 microns thick, which is about 3-4 kÅ more than the trench step height (where 1 micron equals 10 kÅ).
Thicker oxide layers require more polishing to remove excess matter, which lengthens the CMP processing times of FIG.
1
E. Furthermore, post-CMP non-uniformity worsens with longer polishing, since, among other factors, temperature variations across the wafer tend to increase with time during polishing and the removal rate of oxide is a strong function of wafer surface temperature. Other sources of variation include localized wafer regions that are thicker than the rest, leading to“hot spots,” and/or variations in wafer shape during polishing because of stress changes as layers are removed. All of these effects tend to become more severe during longer durations of polishing, resulting in a non-uniform wafer surface after polishing.
SUMMARY OF THE INVENTION
The present invention is directed to techniques for achieving more uniform semiconductor wafers during fabrication of shallow-trench isolation (STI) structures by enabling shorter durations for chemical-mechanical polishing (CMP). According to the present invention,
Kuehne Stephen C.
Maury Alvaro
Shive Scott F.
Blum David S
Mendelsohn Steve
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