Addition overflow detection circuit

Details Addition overflow detection circuit Addition overflow detection circuit

1996-02-06

1998-04-28

Ngo, Chuong Dinh

Boots, shoes, and leggings

36474504, 36478401, G06F 738, G06F 750

Patent

active

057453977

ABSTRACT:
The invention provides an addition overflow detection circuit which can detect an addition overflow at a high rate even where the output bit number is remarkably smaller than the input bit number and which is realized with a comparatively small amount of hardware. An unsigned augend and an unsigned addend of the n bit length are individually divided into lower m bits and upper n-m bits. The lower bits are inputted to an adder, and a carry from the (m-1)th bit to the mth bit is detected from the output of the adder. The upper bits are inputted to both of two fast adder-comparators, by which it is detected that all bits of the sum of them are equal to 1 or 0, respectively. In response to presence or absence of the carry, one of detection outputs of the fast adder-comparators is selected and logically inverted to obtain an overflow detection result.

REFERENCES:
patent: 4768160 (1988-08-01), Yokoyama
patent: 5369439 (1994-11-01), Kim
J. Cortadella et al., "Evaluation of A + B = K conditions Without Carry Propagation", IEEE Transactions on Computers, vol. 41, No. 11, Nov. 1992, pp. 1484-1488.

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